The shift register is a type of sequential logic circuit which is mostly used for storing digital\ndata or the transferring of data in the form of binary numbers in radio frequency identification\n(RFID) applications to improve the security of the system. A power-efficient shift register utilizing\na new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed\nflip-flop has features of high performance and low power. It is composed of a sampling circuit\nimplemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed\nis enhanced by executing four clocked transistors together with a transition condition technique.\nThe simulation result confirms that the proposed topology consumes the lowest amounts of power\nof 30.1997 and 22.7071 nW for parallel in ââ?¬â??parallel out (PIPO) and serial in ââ?¬â??serial out (SISO) shift\nregister respectively covering 22 Ã?¼m2 chip area. The overall design consist of only 16 transistors and\nis simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V\npower supply.
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